1. Field of the Invention
The present Invention relates to a semiconductor integrated circuit, and more specifically to a CMOS dynamic semiconductor integrated circuit.
2. Description of the Prior Art
As illustrated in FIG. 1, a prior art semiconductor integrated circuit comprises an N type transistor Q6, a first logical circuit section 1k, a P type transistor Q7, and a second logical circuit section 1m. transistor Q6 has a source electrode connected to a first reference potential GND (earth potential) and is switched on and off by allowing a clock signal CLK to be inputted to a gate electrode thereof. The first logical circuit section 1k includes a plurality of N type second transistors that are switched on and off by allowing input signals IN1 through INn to be inputted to gate electrodes thereof correspondingly. These transistors are connected between a drain electrode of the transistor Q6 and an output terminal OUT to connect and disconnect the drain electrode of the transistor Q6 and the output terminal OUT with and from each other in conformity with a predetermined logic for the first input signals IN1 through 1Nn. The P type first transistor Q7 has a source electrode connected to a second reference potential VDD (power supply potential point) and is switched on and off by allowing an inverted clock signal CLKb to be inputted to a gate electrode thereof. The second logical circuit section 1m includes a plurality of P type transistors that are switched on and off by allowing the input signals IN1 through INn to be inputted to gate electrodes thereof correspondingly. The logical section 1m is connected between a drain electrode of the transistor Q7 and the output terminal OUT to connect and disconnect the drain electrode of the transistor Q7 and the output terminal OUT with and from each other in a complementary manner with respect to the first logical circuit section 1k, as disclosed in IEEE J, Solid-State Circuit, 1973, pp 462 to 469, "Clocked CMOS Calculator Circuitry".
In the aforementioned semiconductor integrated circuit, the transistors Q6, Q7 are switched on when the clock signal CLK is of a high level. Thereupon, either the logical circuit section 1m composed of the group of P type transistors or the logical circuit section 1k composed of the group of the N type transistors is switched on in conformity with the levels of the input signals IN1 through INn, and hence the output OUT becomes a high or low level. The operation described above is the same as in typical CMOS circuits. When the output signal OUT changes from a high to low level, a conduction path is formed in the logical circuit section 1k between the output terminal and the earth potential through the N type transistors while electrical disconnection is formed between the output terminal and the power supply potential owing to the P type transistors in the logical circuit section 1m. Reverse operation is performed when the output signal OUT is reversed, i.e., from the low to high level. The speed of the just-mentioned change depends upon the capabilities of the associated transistors (channel widths of the transistors).
Once the clock signal CLK goes to low level, the transistors Q6 and Q7 are switched off so that the output terminals are electrically disconnected and isolated from the power supply potential and from the earth potential. At this time, the output signal at the output terminal OUT is kept dynamic in its level immediately before the clock signal CLK is changed to the low level through capacitance connected with the output terminal without depending upon the levels of the input signals IN1 through INn.
In order to speed up the operation of the foregoing semiconductor integrated circuit, it is necessary to increase the channel widths of the transistors of the logical circuit sections 1k and 1m, which causes the input capacitance to be increased.
Such a prior art semiconductor integrated circuit is arranged to drive the two transistors of the logical circuit sections 1k, 1m with use of a single input signal and hence has a drawback that the input capacitance is increased, provided the channel widths of the transistors are widened for the high speed operation. It is therefore required to increase the capabilities of a previous stage driver circuit serving to drive the logical circuit sections 1k, 1m, resulting in the additional problem of increased power consumption. As a result, therefore, it is difficult to obtain the high speed operation. Further, such a prior art semiconductor integrated circuit suffers from a still another difficulty: The inverted clock signal CLKb is required in addition to the clock signal CLK.
Referring to FIG. 2, there is illustrated a second prior art semiconductor integrated circuit which is arranged in the same fashion as in the case of FIG. 1, except that the first transistors Q6, Q7 switched on and off by the clock signals CLK and CLKb are disposed between the logical circuit sections 1m and 1k composed of the second transistors with the output terminal OUT disposed therebetween. Operation of the second prior art example is also the same as in the first case illustrated in FIG. 1. More specifically, when the clock signal CLK is at a high level, the N channel type MOS transistor Q6 and the P channel type MOS transistor Q7 are switched on. At this time, the constituent MOS transistors of the channel P type MOS in the logical circuit section 1m and of the channel N type in the logical circuit section 1k are switched on or off according to the signal levels of the input signal group IN1 through INn to allow the circuit to output a high or low level signal. The operation here is that of a typical CMOS circuit. When the output is changed from the high to low level, a conduction path is formed between the output terminal and the GND electrode owing to the channel N type MOS transistors while electrical disconnection occurs between the output terminal and the VDD electrode. The situation is reversed when the output is changed from the low to high level. Speed of change depends upon the capability of each MOS transistor (channel width of the MOS transistor).
Once the clock signal CLK changes to the low level, the channel N type MOS transistor Q6 and the channel P type MOS transistor Q7 are switched off, so that the circuit is electrically isolated from VDD and GND. At this time, the output is kept dynamic through the capacitance of the output terminal immediately before the clock signal CLK changes to the low level without depending upon the signal levels of the input signal group IN1 through INn.
Also in the prior art semiconductor integrated circuit and likewise the first prior art example, the channel width of each MOS transistor must be widened, causing the input capacitance to be increased, in order to speed up the operation. With the input capacitance so increased, the retardation of signals inputted to the present circuit (input signal group IN1 through INn, clock signal CLK, and inverted clock signal CLKb) will increase. In order to reduce the retardation, the driving capability of a circuit serving to generate such signals must be increased. With the input capacitance increased, electric power consumed by the circuit serving to generate such signal is increased. Since the input signal group IN1 through INn is inputted to both the channel P type MOS transistor group of the logical circuit section 1m and the channel N type MOS transistor group of the logical circuit section 1k, the circuit is severely affected by widening the channel widths of the foregoing transistors.
Furthermore, not only the clock signal CLK, but also the inverted clock signal CLKb is required in order to control the operation state.